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But my point is that the high speed differential signaled pins are not part of the problem. They've actually helped take some of the pressure off of rising die size, which has helped lower the ASP on some parts in recent years. But of course once the external link is a high-speed serial link, you're back to the same problem of rising pin counts in future generation products as more links are added.

All true, but in the CPU and GPU business, we are deep into the problem of pin counts increasing again. You mentioned PCI Express (PCIe). Even though speeds doubled between PCIe 1.0 and PCIe 2.0, again with PCIe 3.0, and will double again in PCIe 4.0, graphics cards have kept in their bandwidth hunger, made worse by systems that support four (officially x16) cards, although most such systems actually provide 8 lanes per card in four card systems. So CPUs may have as many as 36 lanes which can be split to support one and four lane non-graphics cards such as Ethernet and disk controllers.

Even worse are the topology issues with QPI (Intel) or Hypertransport (AMD) CPU interconnects. AMD started out with 3 16-bit wide channels in high-end Opteron CPUs, and two and three hop configurations for four and eight CPU chips per system. Latency has reared its ugly head, and today 8-socket systems use one (8-bit wide) connection between each pair of CPUs. (Hypertransport does work down to 1-bit wide interfaces, with one clock per 8-bit to avoid skew, or up to 32-bits. AFAIK, the only place 32-bit wide HT has been used is to connect two CPU chips in a single package.) Even with speed per channel increases today's CPUs can devote over a hundred pins to three 16-bit wide channels. Add PCIe lanes, and up to four DDR3 memory channels per chip, and it is no surprise that pin counts for high-end CPUs have stuck in the low thousands.
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