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Author: joelcorley Big gold star, 5000 posts Old School Fool Add to my Favorite Fools Ignore this person (you won't see their posts anymore) Number: of 3856  
Subject: Re: IBM Nanotech news Date: 11/2/2012 3:10 AM
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eachus,

You make good points and I know you've been much more involved in the semiconductor side of this field than I have. But I wanted to make one observation about one statement you made, because it could leave a false impression about bond pad counts for uninitiated readers.

You wrote, CPUs and GPUs have thousands of pads, and several hundred each are used for power (Vcc) and ground. Worse, most high-speed signals need differential signalling, which means two wires/connections per signal.

Actually part of the point of the developments in high-speed signaling has been about reducing pin count. High-speed differential signaling tends to lower pin counts because they replace a parallel bus with a high-speed, serial link. Actually this tends to be an Rx/Tx pair on a full duplex link, so the bus gets replaced with 4 pins ... and there may be side-band signals (pins), depending on which technology we're talking about. (Early examples of HSDS were in SCSI and USB. USB 1.x & 2.0 protocols are half duplex, so they only use a single pair and the bus has to be turned around by the host to let the device talk.)

Of course lowering pin count is just a side-effect of the main objective of high-speed differentially signaled serial links. The main object is to improve throughput. The bigger problem with parallel bus architectures is skew. Skew becomes a limiting factor on a parallel bus of any significant length, so external bus technology has gone this route in an effort to increase throughput in any high-speed connections external to the chip. (There are a handful of such high-speed bus protocols, BTW - each targeted at a different application.)

Also some high speed serial links can band together two or more links. (The PCIe protocol refers to each link as a lane.) Banding together such pins will naturally raise pin counts again. However, these solutions use the links asynchronously, so they're not limited by skew as an equivalent parallel bus solutions would have been. So initially this transition is lowering pin counts. However, you can already see that the number of such links is on the rise, so this change has only deferred the problem for a while.

But my point is that the high speed differential signaled pins are not part of the problem. They've actually helped take some of the pressure off of rising die size, which has helped lower the ASP on some parts in recent years. But of course once the external link is a high-speed serial link, you're back to the same problem of rising pin counts in future generation products as more links are added.

- Joel
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