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You wrote,


what would your take be on this....MoS2????


Well first off, I'd point out that while molybdenum isn't cheap or really all that abundant, it's been used in commercial products for years and it's not nearly as expense as so-called precious metals such as gold or titanium. In fact, it looks like its running around $10-20/lbs (it looks like there was a spike to about $35/lbs in 2005), so I suppose you could view it as comparable in cost and scarcity as silver. And silver has been used in some commercial fabrication processes in the past.

Molybdenum production is also quite extensive. North America and China appear to be the two largest producers - each producing on the order of 150M lbs (about 68,000 metric tons) per month. Given that MIT doesn't appear to be proposing this as a substrate material, I suspect its use would only have a small impact on the world's molybdenum supply, even if all chip production transitions to it.

What's more, the processes appears to use existing vapor deposition and etching techniques - efficient and proven technologies. And apparently MoS2 has interesting electrical properties and is easy to work with. The property they find most exciting appears to be the bandgap.

In layman's terms, molybdenum disulfide makes excellent transistors. I actually find this a little ironic. It appears from additional reading that like carbon nanotubes, graphene appears to be a good (2 dimensional) conductor. (I still find it odd to think of carbon as a conductor.) Of course the point of using nanotubes (in the other article) is that they are 3 dimensional structures that will in theory let you construct what are essentially very efficient wave guides. Nanotubes are essentially a single, rolled sheet of graphine. But it also appears graphine might also be an interesting, if less efficient, substitute for nanotubes. (Graphine might also be an interesting choice for vapor deposition and etching.)

So what do I think of it? Well, it's promising technology. Do I think it will take off? Maybe. But currently the size of a transistor isn't (or wasn't the last time I checked) the limiting factor for die size (cost has an almost direct correlation to die size).

There are currently three key limiting factors to die size that I'm aware of. In order of precedence, they are:

1. Bond pad count and size. Lots of chips today are simply limited by the number of pins they expose. Ideally you want none, but that's almost impossible. Usually the minimum is 4, though some devices have hundreds of bond pads. Typical is probably in the 30-60 range.
2. Metal line width. Most fab processes quote minimum feature size; but we're getting to the point where interconnects cost much more of the die than the transistors. And a feature will be something like a structure in a transistor...
3. Via interconnect size. To squeeze in more chip into a small die, designers have been going vertical. But going vertical requires the designer to route a metal line through an interconnect feature known as a via. Vias are much bigger interconnects; but they're use allows you to essentially do place-and-route in three dimensions, making it a trade off between a process fabrication expense the raw expense of the die.

So ultimately this might go somewhere. At least I think I could see this being a technology that could get adopted in future fabrication processes. Will it be? I just can't tell; but I don't see any deal-breakers.

For instance, I don't know if the current or competing technologies scale as well (or better) than MoS2. But more importantly, I think reducing line size (and perhaps bond size and count) are harder problems that need to be solved before this has a chance of being adopted in a process technology... But again, I think this certainly has a chance. And I think it's good R&D. Go MIT!

- Joel
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