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What Joel has to say is about right, but I hope I can make it clearer.

1. Bond pad count and size. Lots of chips today are simply limited by the number of pins they expose. Ideally you want none, but that's almost impossible. Usually the minimum is 4, though some devices have hundreds of bond pads. Typical is probably in the 30-60 range.

CPUs and GPUs have thousands of pads, and several hundred each are used for power (Vcc) and ground. Worse, most high-speed signals need differential signalling, which means two wires/connections per signal.

A lot of work has been done on moving from electronic signals to photons (light). But building semiconductor lasers and detectors on silicon dies is a pain, which is ironic because the fibers in fiber optics are almost pure silicon dioxide. Artificial sapphire (AlO3) wafers are about as cheap as silicon wafers to produce, but the two technologies don't mix well. Gallium arsenide is the technology of the future, always has been, always will be.*

2. Metal line width. Most fab processes quote minimum feature size; but we're getting to the point where interconnects cost much more of the die than the transistors. And a feature will be something like a structure in a transistor...

Actually fab processes are discussed in terms of half-pitch. Take the distance between the left (or right, or top) edge of a line as fine as you can create and the same point on an adjacent line and divide by two. If the lines and spaces are the same width, the half-pitch is the line width. Why get so complex? Because if you make the lines real thin and the gaps wide, you can lay down two sets of lines, one between the other. This double patterning will cut the effective half-pitch in half. When CPU manufacturers talk about chips made with 32, 28, or 22 nm processes, these are all created using double patterning techniques. Does triple patterning exist? Yes, but AFAIK, it is not used in production processes yet.

3. Via interconnect size. To squeeze in more chip into a small die, designers have been going vertical. But going vertical requires the designer to route a metal line through an interconnect feature known as a via. Vias are much bigger interconnects; but they're use allows you to essentially do place-and-route in three dimensions, making it a trade off between a process fabrication expense the raw expense of the die.

In most chips today, all the transistors are on a single level which digs into the bulk silicon a bit. Well the bulk silicon becomes part of the transistor, except in silicon on insulator (SOI) where there is a very thin layer of silicon on top of silicon dioxide SiO2, and both that thin layer and the oxide underneath become an electrical part of the transistor.

The metal interconnect layers used to be aluminium or polysilicon, but today are almost all copper. Aluminium interconnects usually had tungsten vias, copper interconnects have copper vias.

DRAMs tend to have two or three metal layers, CPUs are more likely to have six. Vias on the chips can be the same width as the metal lines, and the resist material or some low-k* filler goes around them. But the metal layers in any fab process are much wider for the top layers than the first metal layer which connects to the actual transistors. If an interconnect has to run a long distance it can be brought to a higher layer to reduce resistance, but that will increase inductance and capacitance. This is one of the areas where carbon nanotubes may be used (see the start of this thread). Carbon nanotubes can replace copper with lower resistance, capacitance and inductance.

Now on to the fun stuff:

Graphene has great promise for electronics, but carbon nanotubes to replace wires will probably come first. (See above.) Making transistors out of graphene is not all that hard but it is not the greatest need today. You have to use a space charge effect to create the needed gap. biasing the charge on the silicon under the two oxide layers in the IBM process would be one way to do that, except that in complex electronics, CMOS which requires adjacent positive (PMOS) and negative (NMOS)

Molybdenum disulphide is most known as an additive to motor oil. But it can be used to make transistors. The advantage of the MIT work is that they can make a single molecule thick layer. (Actually you get a layer which is all moly with one that is all sulfur on top.) This single layer is the goal here. current (extremely small) transistors are made with an area of very pure silicon, with a couple parts per billion of a dopant, to make it into a P or N type semiconductor. Above this is the gate oxide, which used to be simple silicon dioxide, but often now has more silicon nitride, or most recently is made of halfnium oxide or some variant on that. Above the gate oxide is the gate, the third connection to the transistor. (Where is the working part of the transistor? All in the small area under the gate oxide.)

So what is the advantage of MoS2? Remember the SOI (silicon on insulator) above? The advantage is that it makes the working area of the transistor very thin. Smaller volume means less charge to be moved in or out to switch the transistor's state. A single atomic thickness is the holy grail, and MoS2 gets pretty close.

Finally there is one more material to consider. Graphene oxide is almost as thin as graphene, but it is a lot easier to dope than pure graphene. So it may be the winner for extremely thin transistors. But from the users point of view, the initial advantage of any of these materials is that they can replace ITO (Indium Tin Oxide) in flat panel displays. Indium is very expensive, about $750/kilogram. Not as high as gold or platinum, but not cheap. Moly is much cheaper, and carbon and sulfur are basically dirt cheap.

*GaAs is great for reaching very high frequencies, but for most applications it needs to be cooled to liquid nitrogen temperatures. Not practical in consumer goods, although some hobbyists use LN2 to attain real high clock speeds on their (silicon wafer based) computers.
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