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A little while ago, there was debate on this board as to when AMD would have Fab25 and JV3 converted to 110nm production. As I'm back to spending a bit more time on AMD research, I went and did some digging in the AMD press releases, and have a timeline:

December 12 2003: AMD announced the goal of converting Fab25 to 110nm during 2004:

"The far-sighted decision taken back in 2001 to convert Fab 25 from a logic fab to a dedicated Flash memory Fab is validated by the ramp in output from this Fab and the solid execution supporting 170nm in 2002, 130nm today and 110nm technology in 2004," FASL president and CEO Bertrand Cambou said in a statement. "The inclusion of Fab 25 in FASL LLC together with JV1, JV2 and JV3 doubles our total capacity through 2004, establishing a manufacturing powerhouse in Flash memory in support of our customers' business growth."

http://www.internetnews.com/wireless/article.php/3288471

March 17, 2004: AMD announces ramping 110nm to volume production, they are managing (up to) a 30% per-die cost reduction, and 50% more dice per wafer than at 130nm.

SUNNYVALE, CA AND TOKYO -- March 17, 2004 --Spansion™ Flash memory is ramping into volume production on the industry's most advanced production-qualified technology, FASL LLC announced today. Spansion 110-nanometer floating gate technology is the first to push beyond the 130-nanometer barrier in commercial production and features the industry's best price-performance for full-featured, high-density Flash memory. Spansion Flash memory products are manufactured by FASL LLC and available from AMD (NYSE: AMD) and Fujitsu (TSE:6702).

“We believe that Spansion 110-nanometer technology provides the best price-performance for mobile designs and production in 2004,” said Amir Mashkoori, group vice president and general manager of the Wireless Business Unit for FASL LLC. “Leading handset manufacturers are actively building and qualifying products based on Spansion 110-nanometer technology because they understand that our price-performance superiority can directly affect the success of their products. Our customers see unique value in a technology that supports leading-edge products with up to 30% die cost reduction over our previous generation.”

“We aligned efforts throughout our company to optimize our 110-nanometer cost structure and multiply our device manufacturing capacity,” said Jim Doran, executive vice president of worldwide technology development and manufacturing for FASL LLC. “Our manufacturing teams leveraged the experience of our Fab 25 and JV3 facilities, which are exclusively dedicated to leading-edge Flash memory production. Our design teams further optimized this technology to squeeze up to 50% more die on each wafer.”


http://www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_543_2054~83651,00.html

April 20, 2004: Just over a month later, AMD announces that Fab25 has already reached the 50% mark for 110nm production, with nearly-mature yields, and that by midyear nearly 100% of output should be at 110nm:

Spansion today announced that volume production of 110nm floating gate technology in its Austin Fab 25 “MegaFab” now accounts for more than 50 percent of the facility's total production. By midyear, Spansion expects planned output from the facility to be almost exclusively dedicated to 110nm technology.

“Fab 25's near flawless ramp on the 110nm floating gate process is already generating yields well in excess of plans and close to those for mature technologies in full production,” said Randy Blair, vice president, Fab 25. “The combination of excellent yields and a faster than planned production ramp is accelerating our progress to double Spansion Flash memory capacity.”
<snip>

Spansion's second “MegaFab,” JV3 in Aizu-Wakamatsu is expected to follow the same path on 110nm technology in the second half of 2004.


http://www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_543_2054~84494,00.html

After a call to AMD Investor Relations, I confirmed that JV3 was roughly 6 weeks behind Fab25 on conversion to 110nm.

Taking this information together, where are we now?

Fab25 should be producing all (or essentially all) 110nm flash, yielding 40-50% more flash (bitwise) than 6 months ago, at a 20-30% reduction in cost per die.

JV3 should be producing mostly 110nm flash, with full conversion perhaps 4-8 weeks away. Probably yielding 30% more flash (bitwise) than 6 months ago, at a 10% reduction in cost per die - without even accounting for the planned additional production lines to be added to JV3 during 2004.

All in all, a very significant reduction in production costs coupled with a large increase in capacity, particularly of the higher-density, more profitable parts.

Die cost savings alone from Fab25 and JV3 should more than offset any reduction in NOR flash prices over the past 6 months. Increased production from Fab25 and JV3 in a growing NOR flash market should mean greater revenues (particularly if AMD is replacing some of the NOR/NAND/SRAM multi-chip packages it sells with NOR/SRAM MCPs.)

The NOR flash market is growing, apparently in all segments. Intel and AMD are the big dogs, particularly at the high-density end of production. Intel is not seeing a significant increase in sales at the high-density end, leading me to believe that AMD has to be picking up revenue and possibly additional marketshare at the high end.

Finally, do not forget that Q2 2004 was promised to be the first quarter we would see "significant" cost savings from the merger of flash operations with Fujitsu a year ago.

AMD should readily hit $650M in flash revenues for 2Q, if not more.

-Freyj


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Some thoughts on AMD flash technology...
AMD appears to be investing a tremendous amount of money in flash, as they are doing both intermediate technology nodes as well as both NOR and mirrorbit. This means they do 4 flash technology developments for every one of Intels. AMD pretty much got out of the logic technology business with the move of logic development to Fishkill, and mostly IBM resources. I suspect they moved most of the residual logic resources to flash, allowing them this luxery of rapid advanced flash technology development. This leaves AMD very well positioned, technically, in flash for the next several years.
--Alan
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AMD pretty much got out of the logic technology business with the move of logic development to Fishkill, and mostly IBM resources.

I agree with your post, but not with the above sentence. True, the process development (65nm SOI) mostly went to Fishkill, but logic development itself, as in the design/testing/tape-out of K9, is still very much done in-house. From what I understand, the process by itself is useless if the design is not done right.

AMD is still in the logic development business. It's just that now they are sharing process-development costs with IBM, at 65nm and lower.

Marcos
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AMD is still in the logic development business.
Pretty much a matter of semantics. Companies like UMC and TSMC do only the logic technology development and leave the design to other companies like Nvidia. Mentally, I break out the work to do the process development and the product designs. You only need to come out with one new process every two years, while each process will have many, many designs done on it; some will be good, and some will be bad. If the process is bad you are stuck until it is fixed.

I estimate the cost of each leading edge silicon process development in excess of $1B these days, while something like the 90nm shrink of hammer can be done for less than $100M. I do think this is all part of the AMD virtual gorilla strategy to leverage other peoples money...The cost of doing the process development a year behind everybody else is something like a factor of two cheaper in cost, which is one of the reasons the flash technologies tend to lag the logic guys by a year or two.

--Alan
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Pretty much a matter of semantics. Companies like UMC and TSMC do only the logic technology development and leave the design to other companies like Nvidia. Mentally, I break out the work to do the process development and the product designs. You only need to come out with one new process every two years, while each process will have many, many designs done on it; some will be good, and some will be bad. If the process is bad you are stuck until it is fixed.

You'd surely know better than I about this, but what do you make of reports out of IBM where they had great yields with their own chip designs and lousy foundry results on the same process? If AMD is seeing good results with the 90nm CPUs (and I'm not entirely sure they are, as I thought they'd be here a while ago), how did they manage that? (Just by working with IBM more closely than their foundry customers, and borrowing tech from them?)

-A
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You'd surely know better than I about this, but what do you make of reports out of IBM where they had great yields with their own chip designs and lousy foundry results on the same process? If AMD is seeing good results with the 90nm CPUs (and I'm not entirely sure they are, as I thought they'd be here a while ago), how did they manage that? (Just by working with IBM more closely than their foundry customers, and borrowing tech from them?)

Eachus may wish to elaborate on the more technical aspects, but as I understand it, the process and design are intertwined more and more as the geometry shrinks. A "simple" die shrink is a thing of the past as traces and transistors shrink to near quantum size. A good example was the Palimino (180nm) shrink to the T-bred (130nm). It took AMD a year to adjust the design to get decent yeilds and binning, even as they accelerated the 130nm conversion from 9 months to just three. Likewise, the conversion to SOI delayed the Hammer release almost a year. BUT the process was fine, it was the designs that had to change.

IBM designed their chips for the characteristics of the process node on which they planned to run them. My guess is, their foundry customers just tried to take existing designs and do dumb shrinks-and had the same problems as AMD and Intel.

AMD shares process data with IBM, but their designs are their own, so I assume IBM could take an AMD mask set and run with it. Still, the design/process interaction requires a lot of iterationswhen doing the design, which is why AMD partnered with IBM for their 65nm 300mm designs - IBM has a 65nm capable 300mm fab to play with.

Dave



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what do you make of reports out of IBM where they had great yields with their own chip designs and lousy foundry results
It is really a communication, and abilty to follow rules, kind of problem. The process guys document what the process is capable of, and what the designers need to do to eliminate yield loss due to the design. If these rules are not completely documented, or are documented but not followed by the designers, the yields will be bad. IBM designers have been working with IBM processes and associated rules for many, many years. There may be many "implied" rules where "everybody" knows to follow them. IBM certainly does, but how would the foundry customers? I suspect these are some of the reasons IBM is having a difficult time in the foundry business.
--Alan
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